1. Field of the Invention
The present invention relates to a method of implementing low equivalent series inductance (ESL) and controlled equivalent series resistance (ESR) of a multi-layer chip capacitor, and more particularly, to a method of implementing low ESL of a multilayer chip capacitor, which can realize low ESL of the multilayer chip capacitor as well as equivalent series resistance (ESR) controllable up to a high level.
2. Description of the Related Art
In general, a multilayer chip capacitor is used as a capacitive element in a large-scale-integration (LSI) power circuit. Particularly, the multilayer chip capacitor is being widely used as a decoupling capacitor for improving a power transfer characteristic in a power distribution network (PDN) of a microprocessor. To stabilize a power circuit, the decoupling capacitor must have low equivalent series inductance (ESL). Also, development of higher speed microprocessors increases the demands for the lower ESL. Thus, many researches have been conducted to reduce the ESL.
The decoupling capacitor is also required to have controllable equivalent series resistance (ESR) in order to implement more stable power transfer characteristic in the PDN. That is, the decoupling capacitor used in the PDN must have various ESR characteristics that PDN architects can choose from according to their needs. Using a multilayer chip capacitor having ESR lower than a desired level as the decoupling capacitor causes a high impedance peak at a parallel resonant frequency generated by the ESL of the multilayer chip capacitor and plane capacitance of a microprocessor package, and too low impedance at a series resonant frequency of the multilayer chip capacitor. Thus, the low ESR makes it difficult to build the stable PDN.
To lower the ESL, U.S. Pat. No. 5,880,925 discloses a method in which leads of a first-polarity internal electrode and a second internal electrode having opposite polarities are disposed adjacent to each other in an interdigitated arrangement. FIG. 1A is an exploded perspective view illustrating an internal electrode structure of a related art multilayer chip capacitor, and, FIG. 1B is a perspective view illustrating an exterior of a multilayer chip capacitor 10 of FIG. 1A.
Referring to FIG. 1A, internal electrodes 14 are formed on dielectric layers 11a and 11b, respectively. A capacitor body 20 is formed by alternately stacking the dielectric layers 11a and 11b. The internal electrodes 14 are classified into first internal electrodes 12 and second internal electrodes 13. One first internal electrode 12 and one second internal electrode 13 constitute one block, and such blocks are stacked on top of each other. The first internal electrode 12 and the second internal electrode 13 are connected to external electrodes 31 and 32 of FIG. 1B through leads 16 and 17, respectively. The lead 16 of the first internal electrode 12 is disposed adjacent to the lead 17 of the second internal electrode 13 in the interdigitated arrangement. Since voltages of opposite polarities are provided to the adjacent leads 16 and 17, the magnetic flux generated by the high frequency current flowing from the external electrodes 31 and 32 is cancelled between the adjacent leads 16 and 17. Thus, the ESL is lowered.
As shown in FIG. 1A, the first internal electrode 12 has four leads 16 and the second internal electrode 13 also has four leads 17. The resistance generated from the four leads 16 or 17 is connected in parallel, and thus the resistance of the entire multilayer chip capacitor 10 is significantly lowered. The insufficient ESR makes it difficult to meet target impedance and thus makes a power circuit unstable.
In order to prevent the insufficient ESR, U.S. Pat. No. 6,441,459 discloses a method of using only one lead for each internal electrode. However, the current flows in the same direction at some vertically adjacent internal electrodes. Thus, the magnetic flux cannot be cancelled between these adjacent internal electrodes, causing the ESL to increase. Moreover, only using one lead is not enough to meet various demands for ESR characteristics by PDN architects according to their needs.
The multi-terminal multilayer chip capacitor used in the PDN, particularly, for high frequency decoupling must have both very low ESL and controllable ESR up to a high level to stabilize a power circuit. A decoupling capacitor used in a computer central processing unit (CPU) which is one of representative high-speed microprocessors is sometimes required to have ESR of a few ohms (Ω), but it is not easy to implement the ESR of such a high level.